Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs

This tutorial will talk about issues related to performance of arithmetic algorithms when implemented in silicon. Most of the algorithms in use today are based on old and antiquated methods of counting the number of logic gates in the critical path. This produces inaccurate and misleading results. The importance of loading and wire delay is not taken into account by most. As the technology scales further into the sub-micron range, wire starts to dominate the delay. We will show how differed topologies of VLSI adders may influence fan-out and wiring density thus influencing design decisions and yielding to better area/power then known cases. This tutorial will further emphasize a disconnect that exists between algorithms that are used and the final result. The importance of accounting for Fan-In and Fan-Out on the critical path has been demonstrated in Logical Effort (LE) method which can be used for quick speed estimation. However, Logical Effort is not complete if the energy is treated separately. The power is starting to limit the speed of VLSI processors. But, even if we are able to manage the total power, the power density remains a problem.